CFP2 LR4 Transceiver 100G optical transceiver
100G CFP2 Transceiver
100G CFP2 LR4 Transceiver Optical Transceiver 10km
l Compliant with 100GBASE-LR4
l Support line rates from 103.125 Gbps to 111.81 Gbps
l Integrated LAN WDM TOSA / ROSA for up to 10 km reach over SMF
l Digital Diagnostics Monitoring Interface
l Duplex LC optical receptacle
l No external reference clock
l Single 3.3 V power supply
l Case operating temperature range:0°C to 70°C
l Power dissipation < 9W
CFP2 LR4 Transceiver
l Local Area Network (LAN)
l Data Center
l Ethernet switches and router applications
l Compliant to IEEE 802.3ba
l Compliant to CFPMSA CFP2 Hardware Specification
l Compliant to CFPMSA CFP2 Management Interface Specification
FASTFOM 100G CFP2 LR4 Transceiver integrates receiver and transmitter path on one module.
In the transmit side, four lanes of serial data streams are recovered, retimed, and passed to four laser drivers.
The laser drivers control four EMLs (Electric-absorption Modulated Lasers) with center wavelength of
1296 nm, 1300nm, 1305nm and 1309 nm. The optical signals are multiplexed to a single –mode fiber
through an industry standard LC connector. In the receive side, the four lanes of optical data streams are
optically de-multiplexed by the integrated optical de-multiplexer. Each data stream is recovered by a PIN
photo-detector and transimpedance amplifier, retimed. This module features a hot-pluggable electrical
interface, low power consumption and MDIO management interface.
The CFP2 transceiver provides an aggregated signaling rate from 103.125 Gbps to 111.81 Gbps. It is compliant with
IEEE 802.3-2012 Clause 88 100GBASE-LR4 and ITU-T G.959.1-2012-02, and OIF2010.404.08
CEI-28G-VSR electrical specifications. The MDIO management interface complies with IEEE 802.3-2012
Clause 45 standard. The transceiver complies with CFP MSA CFP2 Hardware Specification Rev. 1.0, CFP
MSA Management Interface Specification Rev. 2.2, and OIF CEI-28G-VSR standards.
The CFP2 LR4 Transceiver transmitter path converts four lanes of serial NRZ electrical data from line rate of 25.78 Gbps to 27.95
Gbps to a standard compliant optical signal. Each signal path accepts a 100 Ω differential 100 mV
peak-to-peak to 900 mV peak-to-peak 25 Gbps electrical signal on TDxn and TDxp pins. Inside the module,
each differential pair of electric signals is input to a CDR (clock-data recovery) chip. The recovered and
retimed signals are then passed to a laser driver which transforms the small swing voltage to an output
modulation that drives a EML laser. The laser drivers control four EMLs with center wavelengths of 1296
nm, 1300 nm, 1305 nm and 1309 nm. The optical signals from the four lasers are multiplexed together
optically. The combined optical signals are coupled to single-mode optical fiber through an industry
standard LC optical connector.
The receiver takes incoming combined four lanes optical data from line rate of 25.78 Gbps to 27.95 Gbps
through an industry standard LC optical connector. The four incoming wavelengths are separated by an
optical de-multiplexer into four separated channels. Each output is coupled to a PIN photo-detector. The
electrical currents from each PIN photo-detector are converted to a voltage with a high-gain
transimpedance amplifier. The electrical output is recovered and retimed by the CDR chip. The four lanes
of reshaped electrical signals are output to RDxp and RDxn pins.
Low Speed Signaling
Low speed signaling is based on low voltage CMOS (LVCMOS) operating at a nominal voltage of 3.3 V
for the control and alarm signals, and at a nominal voltage of 1.2 V for MDIO address, clock and data
signals. All low speed inputs and outputs are based on the CFP MSA CFP2 Hardware Specification Rev.
1.0 and CFP MSAManagement Interface Specification Rev. 2.2 requirements.
MDC/MDIO: Management interface clock and data lines.
PRTADR0, 1, 2: Input pins. MDIO physical port addresses.
GLB_ALEMn: Output pin. When asserted low indicates that the module has detected an alarm condition in
any MDIO alarm register.
PRG_CNTL1, 2, 3: Input pins. Programmable control lines defined in the CFP MSA Management
Interface Specification. Pulled up with 4.7 kΩ to 10 kΩ resistors to 3.3 V inside the CFP2 module.
TX_Disable: Input pin. When asserted high or left open the transmitter output is turned off. When
Tx_Dsiable is asserted low or grounded the module transmitter is operating normally. Pulled up with 4.7
kΩ to 10 kΩ resistors to 3.3 V inside the CFP2 module.
MOD_LOPWR: Input pin. When asserted high or left open the CFP2 module is in low power mode. When
asserted low or grounded the module is operating normally. Pulled up with 4.7 kΩ to 10 kΩ resistors to 3.3
V inside the CFP2 module.
MOD_RSTn: Input pin. When asserted low or grounded the module is in Reset mode. When asserted high
or left open the CFP2 module is operating normally after an initialization process. Pulled down with 4.7 kΩ
to 10 kΩ resistors to ground inside the CFP2 module.
PRG_ALRM1, 2, 3: Output pins. Programmable alarm lines defined in the CFP MSA Management
Mod_ABS: Output pin. Asserted high when the CFP2 module is absent and is pulled low when the CFP2
module is inserted.
RX_LOS: Output pin. Asserted high when insufficient optical power for reliable signal reception is
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